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EZ-Extender Hardware Reference
The EZ-Extender holds two clock signals, TX_CLK and RX_CLK . The TX_CLK
signal is used as an output to the interface you are using. The TX_CLK sig-
nal can be generated in three ways: applying a signal via an SMA
connector, populating a socket with an oscillator, or using a 27 MHz sig-
nal provided by the EZ-KIT Lite. Only one of these sources can be used at
a time, the other sources must be disabled. For how to disable the TX_CLK
sources, see “SMA Connector Clock Disconnect Jumper (P10)” on
page 2-9 and “External Clock Disable Jumper (P37)” on page 2-10 . The
RX_CLK signal is generated by the target board. Both the TX_CLK and
RX_CLK can connect to the PPI_CLK signal as an input to the processor. See
“Clock Routing Switch (SW2)” on page 2-5 for more information.
The ADC/mixed-signal HSC interface and camera interface have two
frame sync signals, FSYNC1 and FSYNC2 . For information on how to set the
direction and the source of these signals, refer to “Direction Control
Switch (SW1)” on page 2-4 and “General Frame Sync Routing Switch
(SW3)” on page 2-7 .
The LCD interface has two frame sync signals, FSYNC1_LCD and
FSYNC2_LCD . These signals are always outputs, but it is possible set the
source of the signals. For more information see, “LCD Frame Sync Rout-
ing Switch (SW4)” on page 2-8 .
The ADC/mixed-signal HSC interface and camera interface connect to
the DATA_A[15:0] parallel bus. The DAC HSC interface and the LCD
interface connect to the DATA_B[15:0] parallel bus. The DATA_A bus is
attached to only the PPI0 bus, while DATA_B[15:0] can connect to either
PPI0 or PPI1 busses. This allows access to all of the interfaces with a single
PPI port or access to two separate interfaces with two PPI ports. For more
information about the routing of the PPI data signals see, “PPI Data
Routing Jumper (P36)” on page 2-9 . To configure the direction of the
DATA_A signals, see “Direction Control Switch (SW1)” on page 2-4 .
Blackfin EZ-Extender Manual
2-3
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